The present invention relates to a virtual ground type semiconductor storage device.
In recent years, the capacities of semiconductor storage devices have been remarkably increased, and in order to cope with cost reduction, devices having a reduced effective cell area, such as the multi-valued system and the virtual ground system, have been introduced into the market one after another. In particular, the virtual ground system, which can achieve a small cell area merely by designing the circuit appropriately, allows the development of a device of a smaller chip area than the other systems even through the same process.
However, in the virtual ground system, because the drains and sources of memory cell transistors arranged in two adjacent columns are commonly connected to an identical virtual bit line, a leak current from the adjacent cells cannot be ignored. Therefore, to eliminate the effect of the leak current, according to devices that have been produced so far, a read operation is executed every eight bits in eight sense operations (prior art 1), as disclosed in Japanese Patent Laid-Open Publication No. HEI 6-68683.
Alternatively, the threshold voltage of memory cell transistors of every ninth bit is made higher than the threshold voltage (corresponding to stored data "0", "1") of the other memory cell transistors, thereby preventing the leak current (prior art 2).
FIG. 9 shows one block of a memory cell array disclosed in the Japanese Patent Laid-Open Publication No. HEI 6-68683. When reading data stored in a memory cell 1, a diffusion virtual ground line selection line 12 and a diffusion bit line selection line 10 as well as a word line 4 are pulled up to Vcc simultaneously, while a diffusion virtual ground line selection line 13 and a diffusion bit line selection line 11 are made to have the ground level. Then, a metal virtual ground line 15 is pulled down to the ground level by the operation of a pre-charge selection circuit 14, so that diffusion virtual ground lines 6 and 7 come to have the ground level. On the other hand, the other metal virtual ground lines 17, . . . come to have a pre-charge voltage Vpc by the operation of the other pre-charge selection circuits 16, 16, . . . , so that the other diffusion virtual ground lines 5, 8, 9, . . . come to have the pre-charge voltage Vpc. Also, a metal bit line 19 is selected by a Y-gate 18. Then, the diffusion bit line selection line 10 is pulled up to Vcc, and a diffusion bit line 3 is placed in a selected state since the diffusion bit line selection line 11 has the ground level.
In this state, the potential of the diffusion bit line 3 varies as shown in FIG. 10 depending on the data retained in the memory cell 1 and its adjacent memory cell 2. Therefore, by setting the inversion level of the sense amplifier to a position, indicated by the arrow, located lower than a level of (Vpc--Vth) and higher than a level approximately intermediate between (Vpc-Vth) and Vpc/2, the data retained in the memory cell 1 can be read regardless of the state of the adjacent memory cell 2. Subsequently, four diffusion bit lines are successively selected by means of the Y-gate 18 and diffusion bit line selection lines 10 and 11, and during this operation the voltages on the diffusion virtual ground line selection lines 12 and 13 are switched over for the inversion of the voltages applied to the diffusion virtual ground lines. Thus, the data retained in all the memory cells connected to one word line are read in eight sense operations.
However, the above prior art virtual ground type semiconductor storage devices have the following problems. That is, the semiconductor storage device disclosed in the Japanese Patent Laid-Open Publication No. HEI 6-68683 (prior art 1) necessitates eight sense operations as described above in order to read the data stored in all the memory cells connected to one word line. Therefore, it takes much time to read the stored data, so that a high-speed read operation is impossible.
On the other hand, in the second semiconductor storage device (prior art 2), invalid memory cells each constructed of a transistor having a threshold voltage higher than the threshold voltage of the normal memory cell transistor are arranged at intervals of eight bits, and this leads to a problem that the effective memory cell area is increased.